The present invention relates to a central processing unit of a computer and more particularly to an instruction fetch device for predicting a branch destination of a branch instruction by supplying fixed-length part of a variable-length instruction.
FIG. 8 shows the construction of a conventional instruction fetch device for performing a branch destination prediction. In the Figure, numeral 7 designates a 29-bit read pointer for holding the leading address of an instruction code to be read, 8 an instruction cache, and 9 a branch history table for storing as a set the address of each branch instruction taken and the address of the branch destination. The address of an instruction code to be read is stored in the read pointer 7 and the instruction cache 8 and the branch history table 9 are searched. When the instruction code read out from the instruction cache 8 includes any branch instruction taken in the past, it is expected that its branch destination address is also read from the branch history table 9. In this case, this branch destination address is read and stored in the read pointer 7 and the instruction cache 8 is searched thereby reading the instruction code at the branch destination without waiting until the decoding and execution of the branch instruction.
However, where branch instructions Bcc0 and Bcc1 are respectively present at the positions of addresses n and n+4 as shown in the instruction alignment diagram in FIG. 9A, after the high-order 29 bits of the address n have been stored in the read pointer 7, even if the branch history table 9 is searched by the high-order 29 bits of the address n so as to obtain the branch destination address of the branch instruction Bcc0 or Bcc1, both of the two entries storing the branch destination addresses hit and thus the desired branch destination address cannot be obtained. Also, where an instruction OP with a 32-bit displacement operand disp 32 is present at the position of an address n+6 as shown in the instruction alignment diagram in FIG. 9B, in predicting a branch instruction for branching to the address n+6 from a certain address, even if the branch destination address obtained from the branch history table 9 is the address n+6, the instruction code read from the instruction cache 8 does not include the displacement operand disp 32 and a wait is required for the decoding of the instruction OP until the displacement operand disp 32 is read out again.